Ultra-thin diffusion barrier

ABSTRACT

A metal interconnect arrangement in an integrated circuit, includes a damascene trench which includes a dielectric base, with a trench made therein, one or more two dimensional diffusion barrier layers formed over the trench, a conductor layer formed atop the diffusion layer, wherein the one or more two-dimensional diffusion barrier layers substantially prevent diffusion of constituents of the conductor layer into the dielectric base.

STATEMENT REGARDING GOVERNMENT FUNDING

This invention was not made with Government Support.

TECHNICAL FIELD

The present disclosure generally relates to placement of interconnect metal in integrated circuits, and in particular, to placement of copper and an associated ultra-thin diffusion barrier.

BACKGROUND

This section introduces aspects that may help facilitate a better understanding of the disclosure. Accordingly, these statements are to be read in this light and are not to be understood as admissions about what is or is not prior art.

Copper is preferred to aluminum for choice of material for interconnect metals in integrated circuits owing to its higher conductivity. However, while aluminum can be deposited using typical deposition processes, copper is typically deposited using an electroplating process. In doing so, trenches (typically called Damascene) are made into oxide and copper is then deposited into the trenches. Any over-deposition of copper (typically referred to as overburden) is removed using various techniques (e.g., chemical-mechanical planarization (CMP)). One issue with deposition of copper in these trenches is diffusion of copper atoms into the oxide layer generating traps deep into the oxide, thereby degrading the insulating properties of the oxide. In particular, copper diffusion into the dielectric between two interconnects can cause shorting and create chip failures, while diffusion to transistors can introduce deep-level traps to Si and affect overall transistor performance.

To prevent this phenomenon, prior to deposition of copper, a diffusion barrier layer is placed on the trenches. The diffusion barrier layer prevents diffusion of copper atoms into the oxide. The diffusion layer must have at least three properties: 1) provide a chemical barrier for copper atoms to diffuse into the oxide layer, 2) provide high electrical conductivity between the oxide and the later-deposited copper layer, and 3) be as thin as possible, since the electrical conduction of copper is directly proportional to its thickness (cross-sectional area) and thicker diffusion barrier layer means thinner copper. The diffusion barrier layer needs to be provided on all sides of the copper deposited to prevent the aforementioned deleterious effects. While aluminum also required a diffusion barrier layer, such was not required on all sides. Therefore, with copper, the diffusion barrier layer results in a significant lowering of the available copper that can be deposited.

Traditionally, various materials are used to provide a diffusion barrier layer. One such material is TaN which is placed on the trench as a diffusion barrier layer, but because of its poor adhesion to Cu a layer of Ta is then deposited on the TaN. The typical overall thickness of the diffusion barrier-adhesion layer can range to 4-5 nm. This thickness poses a serious challenge, since as mentioned above, more of TaN means less copper, and hence less conduction.

As geometries shrink, available thickness for copper as a choice for the interconnect material becomes more tenuous. In particular, the aforementioned challenges are exasperated since the interconnect half-pitch size will reach about 20 nm in the coming sub-5 nm technology node. Meanwhile, the TaN/Ta diffusion barrier-adhesion layer stack has to be greater than 4 nm to provides acceptable properties for both limiting diffusion as well as enhancing adhesion (i.e., anything thinner will suffer from proper diffusion barrier properties for which the layers are used). However, as alluded to above, since the diffusion layer-adhesion layer of TaN/Ta result in a significant available volume of the interconnect cross-section, little is left for copper as the interconnect metal, thus preventing shrinking geometries to a desirable scale (e.g., sub-5 nm scale).

Past attempt to deposit thinner diffusion layers of TaN using atomic-layer-deposition (ALD) have resulted in diffusion layers that provide less than desirable performance. Along the same line, 2D structures (i.e., atomically deposited material) have also been investigated in the prior art such as graphene, molybdenum disulfide (MoS₂), and hexagonal boron nitride (h-BN), however, these materials are deposited utilizing processes such as chemical vapor deposition with deposition temperatures that prove to be deleterious for other structures requiring a metallic substrate and follow-on transfer from the metallic substrate to the dielectric substrate which present additional challenges making such approaches unpractical.

Therefore, there is an unmet need for a novel approach to replace exiting diffusion barrier-adhesion barrier with a new one that meets the goals listed above.

SUMMARY

A metal interconnect arrangement in an integrated circuit is disclosed. The metal interconnect arrangement includes a damascene trench. The damascene trench includes a dielectric base, with a trench made therein. The damascene trench further includes one or more two dimensional diffusion barrier layers formed over the trench. The damascene trench further includes a conductor layer formed atop the diffusion layer. The one or more two-dimensional diffusion barrier layers substantially prevent diffusion of constituents of the conductor layer into the dielectric base.

A method of providing a barrier to diffusion of metal into a dielectric in a metal interconnect arrangement is also disclosed. The method includes forming a damascene trench which includes forming a dielectric base, with a trench made therein. The formation of the damascene trench further includes depositing one or more two dimensional diffusion barrier layers formed over the trench. The formation of the damascene trench further includes depositing a conductor layer formed atop the diffusion layer. The one or more two-dimensional diffusion barrier layers substantially prevent diffusion of constituents of the conductor layer into the dielectric base.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a cross-sectional view of a damascene trench within a dielectric with a three-dimensional bilayer diffusion barrier layer/adhesion layer (barrier/liner) and an interconnect metal deposited therein and capped with a capping layer.

FIG. 2 is a graph of line resistance increase (%) as a function of barrier/liner thickness (nm) for interconnect widths in nm.

FIG. 3 is a schematic of a fabrication setup of the novel diffusion barrier of the present disclosure showing a chemical vapor deposition chamber equipped with a plasma generator and a furnace.

FIG. 4 is a chemical schematic of Ta atoms shown to make a crystalline structure with S radicals.

FIG. 5 is a perspective view of an experimental setup for a surface scattering measurement.

FIG. 6 represent graphs of cumulative probability vs. copper resistivity measured in μΩ-cm is shown.

FIG. 7 represent schematic depiction of wettability experiments for Cu formed on dielectric, Cu formed on Ta, and Cu formed on TaS_(x).

FIG. 8a represent a series of schematics showing an adhesion test, according to the present disclosure.

FIG. 8b is a schematic of a test setup for a 4-probe bending test.

FIGS. 9 and 10 represent graphs of cumulative probability vs. time-to-breakdown, (t_(BD)) in seconds (industry standard approach for showing diffusion activity) for TaS_(x) compared to TaN with a thickness of 2 nm and SiO₂ in FIG. 9, and compared to Ta with thicknesses of 1.5 nm and 3 nm in FIG. 10 with TaS_(x) having a thickness of 1.5 nm.

FIG. 11 is a schematic of molecular interactions of Cu or Cu ions with TaS₂ in the forms of grain boundary diffusion and interlayer diffusion.

FIG. 12 are cross-sectionals view of damascene trenches (prior art in the left panel and the novel arrangement of the present disclosure in the right panel), where in the right panel the thinner TaS_(x) results in a much larger copper volume.

DETAILED DESCRIPTION

For the purposes of promoting an understanding of the principles of the present disclosure, reference will now be made to the embodiments illustrated in the drawings, and specific language will be used to describe the same. It will nevertheless be understood that no limitation of the scope of this disclosure is thereby intended.

In the present disclosure, the term “about” can allow for a degree of variability in a value or range, for example, within 10%, within 5%, or within 1% of a stated value or of a stated limit of a range.

In the present disclosure, the term “substantially” can allow for a degree of variability in a value or range, for example, within 90%, within 95%, or within 99% of a stated value or of a stated limit of a range.

A novel approach to replace exiting diffusion barrier-adhesion barrier with a new structure that meets the following goals is presented in the present disclosure: 1) provide a chemical barrier thereby preventing copper atoms from diffusing into the surrounding oxide layer, 2) provide high electrical conductivity between the oxide and the later-deposited copper layer, and 3) be ultra-thin so that more copper can be deposited resulting in higher conduction. To this end, the present disclosure presents use of TaS_(x) as one or more two dimensional diffusion barrier layers as a replacement diffusion barrier layer which has been shown to be as low as 0.7 nm in comparison to 4-5 nm of existing three-dimensional diffusion barrier layers (e.g., TaN as a diffusion barrier layer with Ta deposited on TaN for additional adhesion). According to the present disclosure, then, the 2D layered of tantalum sulfide (TaS_(x)) with a thickness of about 0.7 nm thickness is developed that can be deposited using a single or more layers (e.g., two layers each providing about 0.7 nm thickness) to replace the conventional TaN/Ta bilayer. The TaS_(x) ultra-thin film is compatible with traditional integrated circuit fabrication processes and based on the methods discussed herein can be directly deposited on dielectrics thereby removing the need to detach from an interim substrate and placement on the final substrate. Results presented in the present disclosure provide superior diffusion barrier qualities (at least about as good as TaN or Ta), while allowing a significant more volume of copper as the interconnect metal in the interconnect channel. The TaS_(x) 2D material discussed in the present disclosure further provides superior adhesion to copper (at least as good as Ta), thus eliminating the need for additional adhesion layers (e.g., Ta). As a result, the TaS_(x) structure of the present disclosure provides additional runway for interconnects for smaller geometries (e.g., beyond the 5 nm scaling).

Referring to FIG. 1, a cross-sectional view of a traditional damascene trench 100 within oxide 102 is shown with a bilayer TaN—Ta diffusion barrier layer (barrier/line) 110 including a barrier layer of TaN 104 and an adhesion layer 106 with the copper 108 deposited therein and capped with a capping layer 112. As discussed for 5 nm technology, the thickness (therefore, the cross-sectional area) of the copper interconnect 108 is on the same order as the bilayer 110, resulting in a significantly higher resistance. This relationship is shown in FIG. 2, which is a graph of line resistance increase (%) as a function of barrier/liner thickness (nm) for interconnect widths in nm. As shown in FIG. 2, as the barrier/liner thickness (thickness of the bilayer 110) increases towards 4-5 nm which is the current regime in conventional fabrication techniques, the line resistance increases significantly starting about 3 nm for any of the three widths 28 nm, 16 nm, and 12 nm (e.g., 50-75% for 28 nm width, 150-225% for 16 nm width, and off the chart for 12 nm). This increases is contrasted with a 2D material of the present disclosure (TaS_(x)) which has been shown to effectively perform the functionality of the diffusion barrier bilayer 110 but have a thickness of only between about 0.7 nm to 1.5 nm, with respect to which, the line resistance of the interconnect increases quote moderately (between about 5-10% for the 28 nm width, 5-25% for the 16 nm width, and 5-30% for the 12 nm width.

Thus, according to the present disclosure a novel approach is presented that replaces TaN/Ta, representing the current standard for integrated circuit fabrication industry for diffusion barrier-adhesion material for interconnects, to a 2D layered material, namely tantalum sulfide (TaS_(x)), to serve as an ultra-thin 2D structure barrier that needs no additional adhesion layer. The about 0.7 nm thick polycrystalline TaS_(x) film is deposited on substrates at temperatures that are compatible with ban-end-of-line (BEOL) technology. The present disclosure provides comparison between (i) Ta and TaS_(x) for adhesion properties and (ii) TaN and TaS_(x) for diffusion barrier properties. As discussed above, actual reduction to practice of TaS_(x) structures provide good results showing the TaS_(x) structure provide both superior liner and barrier properties simultaneously, all the while reducing the thickness to allow significant more copper metal deposition. These results are found in contrast to the conventional TaN/Ta diffusion barrier layer-adhesion layer which includes two layers each thicker than the single or double layers of the TaSx of the present disclosure as shown in FIG. 2, which is a graph of barrier/liner (i.e., TaN/Ta in case of the conventional approach) vs. line resistance increase (as a measure of percentage increase) for different wire thicknesses (the direction of arrow shows decreasing wire thicknesses). In the lower barrier/liner thickness zone (i.e., 0.5-1.5 nm), the material in the highlighted strip is considered to be in the 2D range. The highlighted portion on the right represents the conventional barrier/liner (i.e., TaN/Ta) which is in the range of 4-5 nm.

While, as discussed in the background section, some investigators had attempted to make 2D structures in order to maximize copper interconnect volume, such efforts required processing that were incompatible with BEOL processes. To this end, according to the present disclosure a different process and material are chosen as compared to the prior art. In particular, TaS_(x) is chosen (where x is between 1.5-2.5) as the barrier/liner material while plasma-enhanced-chemical-vapor-deposition (PECVD) is chosen as the BEOL-compatible process. The PECVD process is run a lower temperature since it uses plasma. Referring to FIG. 3, a schematic of the fabrication setup of the novel diffusion barrier is presented showing a chemical vapor deposition chamber equipped with a plasma generator and a furnace, wherein a window is cut open to show the interior of the chamber showing Ar atoms (provided as an input to the chamber) as well as hydrogen and sulfur radicals (disassociated from H₂S which was provided as input to the chamber). By utilizing the system of FIG. 3, actual reduction to practice was made possible for centimeter-scale, uniform TaS_(x) prepared by converting a polycrystalline Ta film in a hot-zone furnace as illustrated in FIG. 3. A Ta film was pre-deposited on a Si/SiO₂ substrate by an e-beam evaporator technique, known to a person having ordinary skill in the art. Hydrogen sulfide (H₂S) was used as the precursor while Ar was used as the carrier gas. The flow rates for both gases were about 10 sccm. The growth temperature was set at about 400° C. The growth time was set at about 20 minutes. The plasma power was set at about 70-80 W. During the growth process, the remote plasma dissociate H2S into H and S radicals. S radicals react with Ta and convert Ta to TaS_(x), resulting in a TaS_(x) film. The mechanism of conversion is illustrated in FIG. 4 where schematically Ta atoms are shown to make a crystalline structure with S radicals. An example is 1T-tantalum disulfide (TaS₂).

To understand the interface between TaS_(x) and copper, the impact of TaS_(x) on the surface scattering of copper interconnects was first studied. Towards this goal, the surface scattering at the SiO₂/Cu, Ta/Cu, and TaS_(x)/Cu interfaces were studied. Ultra-thin Cu films with thicknesses of about 15 nm were deposited on exemplary surfaces such as SiO₂, Ta, and TaS_(x). Thin films of copper were provided in Kelvin structures, known to a person having ordinary skill in the art, for accurate resistance measurements, as illustrated in FIG. 5 which is a perspective view of an experimental setup for the aforementioned surface scattering measurements. In this set up, a dielectric Si/SiO₂ is provided as a base, on which a liner is optionally placed (the liner can be Ta or TaS_(x)), and on top of the liner is a layer of copper as discussed above. The resistivity of the devices shown in FIG. 5 were measured and the results are presented in FIG. 6. Referring to FIG. 6, graphs of cumulative probability vs. copper resistivity measured in μΩ-cm is shown. While for macro-structures resistivity is a function of material properties, in ultra-small dimensions, such as the dimensions discussed herein, resistivity changes with changes in dimensional scales. For example, resistivity increases as dimensions decreases in these ultra-small dimensional regimes. Therefore, while Cu resistivity increases as corresponding dimensions decrease, the Cu with smallest dimension (13 nm) on TaS_(x) has the lowest resistivity among the three groups, indicating a more specular/elastic interface scattering. The inferior conductivity of Ta/Cu and SiO₂/Cu are attributed to the perturbing localized interfacial states. Conversely, the weaker interaction between 2D layered materials and Cu results in a diminished perturbation at the interface. AS a result, the Cu/TaS_(x) results in a more robust resistivity and thus resistance for the copper interconnect.

In addition to the surface scattering discussion provided above, two other attributes play important roles in choice of TaSx as the material of choice for the interconnect material. The two additional attributes are wettability and adhesion of Cu to TaS_(x). Wettability is an attribute in order to provide a good surface for the Cu seeding layer. Wettability is also important for the subsequent electroplating of Cu. Adhesion is important for Cu to survive chemical-mechanical polishing (CMP) processes. Adhesion also effects electromigration lifetime of Cu wires.

In order to determine how TaS_(x) affects wettability, ultra-thin films of Cu (about 10 nm) were deposited on different surfaces. Referring to FIG. 7, results of these test are shown. FIG. 7 includes three panels which show Cu on SiO₂, a dielectric (left panel), Cu on Ta (middle panel), and Cu on TaS_(x). Inspecting FIG. 7, the left panel shows many cracks on the Cu film deposited on SiO₂ (i.e., no liner. These cracks represent poor wettability for Cu on SiO₂ . In comparison, Cu on Ta and Cu on TaS_(x) both exhibit good wettability (middle and right panels, respectively). Therefore, the wettability test indicates as good of performance as industry standard (i.e., Ta) for adhesion layer as that for TaS_(x).

In order to determine adhesion properties of TaS_(x), a tape test method, known to a person having ordinary skill in the art . In this test, after a thin layer of Cu is deposited on a surface it is picked up using an adhesive tape. The adhesion test evaluates how much of the Cu layer separates from the test surface. In this case, after TaS_(x) has been prepared partially on the SiO₂ substrate, about 80 nm of Cu is deposited on TaS_(x) and SiO₂ . Thereafter, a length of 3M Scotch Tape is used for the aforementioned adhesion test. After the tape is picked up, as shown in FIG. 8a (a series of schematics showing the adhesion test), Cu was picked up from all areas except for areas with TaS_(x). As shown in the right panel of FIG. 8a , Cu on SiO₂ regions was detached by the tape, while Cu remained on the TaS_(x).

Since wettability of Cu/TaS_(x) is as good as industry standard (Cu/Ta) and since adhesion test shows robust adhesion between Cu and Cu/TaS_(x), in totality, TaS_(x) is a good candidate for a Cu as an interconnect metal.

Lastly, in order to show as good of diffusion barrier attribute as the industry standard (TaN) for TaS_(x), a time-dependent dielectric breakdown (TDDB) measurements methodology, known to a person having ordinary skill in the art was used. TDDB measurement is a standard test method to evaluate gate dielectric reliability as well as Cu diffusion in the dielectrics or IMDs of interconnects. To this end, a capacitor structure is utilized for TDDB measurements to study the intrinsic diffusion barrier properties of TaS_(x). Breakdown resulting from the CMP process (discussed above) can occur in interconnect damascene structures. Such breakdowns affect choice of a new material for the diffusion barrier property. Thus, in totality the TDDB measurements as well as the adhesion and wettability measurements for TaS_(x) show it to be as good or even better than TaN/Ta, the industry standard for a diffusion barrier layer and adhesion layer.

It is understood that TaN in the TaN/Ta bilayer discussed above, provides the primary function of diffusion barrier of Cu into the dielectric, while Ta primarily functions as an adhesion layer. However, it is also understood that Ta may also provide some diffusion barrier functionality. FIGS. 9 and 10 provide graphs of cumulative probability vs. time-to-breakdown, (t_(BD)) in seconds (industry standard approach for showing diffusion activity) for TaS_(x) compared to TaN with a thickness of 2 nm and SiO₂ in FIG. 9, and compared to Ta with thicknesses of 1.5 nm and 3 nm in FIG. 10 with TaS_(x) having a thickness of 1.5 nm. Inspecting FIGS. 9 and 10, the graphs indicate that TaS_(x) with a thickness of 1.5 nm performs as good as TaN with a thickness of 2 nm and as good as Ta for a thickness of 3 nm (said thicknesses for TaN and Ta being necessary to ensure proper bilayer structure discussed above).

Based on the experimental results shown in FIGS. 9 and 10, then, comparing TaS_(x) diffusion barrier qualities to that of TaN and Ta in bilayer structure, the present disclosure proposes a 5 nm TaN/Ta stack (2 nm TaN+3 nm Ta) can be substituted with a 3 nm TaS_(x) layer or thinner—a further improvement of film quality can reduce TaS₂ thickness to 0.7 nm (single-layer TaS₂) while maintaining or even improving the barrier/liner performance of 5 nm TaN/Ta bilayer.

Energy barrier of TaS2 is comparable to TaN while providing significant reduction in thickness. Further scaling can be achieved given the 2D material nature of TaS_(x). A graphical explanation for the higher energy barrier is provided in FIG. 11, where a schematic of molecular interactions of Cu or Cu ions with TaS₂ in the forms of grain boundary diffusion and interlayer diffusion is shown. Thus, a schematic of the aforementioned significant resistance reduction benefitting owing to enlargement of Cu volume is provided in FIG. 12, where in the left panel, the prior art Ta/TaN is shown as the diffusion/adhesion layers and in the right panel and thinner TaS_(x) only layer is shown as the diffusion barrier resulting in a much larger copper volume.

The novel material of the present disclosure is made according to the following non-limiting exemplary method. As an initial step, Ta is deposited using an e-beam evaporator process, known to a person having ordinary skill in the art. This deposition step deposits Ta on Si/SiO₂ as a substrate. Next, the substrate with Ta deposited thereon, is placed into a PECVD chamber (see FIG. 3). Thereafter, the furnace (shaped in the form of a tube) is pumped down to about 10 mTorr. Thereafter, nitrogen is pumped through the furnace to purge any unwanted gases. These steps of pumping down and purging using nitrogen are repeated a plurality times (e.g., ten times) to remove moisture, unwanted gases and particles, and other possible contamination that might have been introduced from ambient during the sample loading step. At the same time as the pump down/purging process is repeated, the temperature of the furnace is set at about 200 to 800° C. or for BEOL-compatible processes 400° C. This temperature can be in a bout 5-10 minutes depending on the furnace. Once the desired temperature is reached, the furnace is pressurized to a base pressure of about 10 mTorr. At the same time, Ar at a flow rate of about 10 sccm to about 100 sccm is introduced into the furnace. With increasing temperature pressure at within the chamber raises to about 180 mTorr. Thereafter, H₂S with a flow rate of 10 sccm is introduced allowing the pressure to reach about 320 mTorr from 180 mTorr. After waiting for about 5 minutes to allow stabilization of temperature and flow rate, plasma power is activated and slowly allowed to increase to about 70 W. With the application of plasma, the pressure increases from 180 mTorr to about 420 mTorr. At this point, H₂S reacts with Ta to generate TaS_(x). After about 20 minutes of reaction and therefore growth, the plasma is turned off, followed by turning off the gases and the furnace heater.

It should also be appreciated that Ta and Ti represent choices of materials used in interconnect structures, as known to a person having ordinary skill in the art. As such other suitable materials based on the present disclosure are within the scope of the present disclosure. In particular, it is within the scope of the present disclosure to substitute TaS₂ with other compounds with similar structures. Examples include TaSe₂, TaTe₂, TiS₂, TiSe₂, and TiTe₂. These compounds behave in similar fashion as TaSx in providing as good or better diffusion barrier, wettability, and adhesion as TaN/Ta, but at a smaller thickness, allowing a larger copper volume in the damascene trench.

Those having ordinary skill in the art will recognize that numerous modifications can be made to the specific implementations described above. The implementations should not be limited to the particular limitations described. Other implementations may be possible. 

1. A metal interconnect arrangement in an integrated circuit, comprising: a damascene trench, including a dielectric base, with a trench made therein, one or more two dimensional diffusion barrier layers formed over the trench, a conductor layer formed atop the diffusion layer, wherein the one or more two-dimensional diffusion barrier layers substantially prevent diffusion of constituents of the conductor layer into the dielectric base.
 2. The metal interconnect arrangement of claim 1, wherein the dielectric base is SiO₂ .
 3. The metal interconnect arrangement of claim 2, wherein each of the one or more two-dimensional diffusion barrier layers is TaS_(x).
 4. The metal interconnect arrangement of claim 3, wherein x is
 2. 5. The metal interconnect arrangement of claim 3, wherein x is between 1.5-2.5.
 6. The metal interconnect arrangement of claim 3, wherein the conductor layer is copper.
 7. The metal interconnect arrangement of claim 3, wherein thickness of each of the one or more two-dimensional diffusion barrier layers is about 0.7 nm.
 8. The metal interconnect arrangement of claim 3, wherein the one or more two-dimensional diffusion barrier layers consists of a single layer of TaS_(x).
 9. The metal interconnect arrangement of claim 3, wherein the one or more two-dimensional diffusion barrier layers consists of two layers of TaS_(x).
 10. The metal interconnect arrangement of claim 3, wherein diffusion barrier properties of the one or more two-dimensional diffusion barrier layers is about equal to a bilayer of TaN/Ta having a thickness of about 5 nm.
 11. A method of providing a barrier to diffusion of metal into a dielectric in a metal interconnect arrangement, comprising: forming a damascene trench, including forming a dielectric base, with a trench made therein, depositing one or more two dimensional diffusion barrier layers formed over the trench, depositing a conductor layer formed atop the diffusion layer, wherein the one or more two-dimensional diffusion barrier layers substantially prevent diffusion of constituents of the conductor layer into the dielectric base.
 12. The method of claim 11, wherein the dielectric base is SiO₂ .
 13. The method of claim 12, wherein each of the one or more two-dimensional diffusion barrier layers is TaS_(x).
 14. The method of claim 13, wherein x is
 2. 15. The method of claim 13, wherein xis between 1.5-2.5.
 16. The method of claim 13, wherein the conductor layer is copper.
 17. The method of claim 13, wherein thickness of each of the one or more two-dimensional diffusion barrier layers is about 0.7 nm.
 18. The method of claim 13, wherein the one or more two-dimensional diffusion barrier layers consists of a single layer of TaS_(x).
 19. The method of claim 13, wherein the one or more two-dimensional diffusion barrier layers consists of two layers of TaS_(x).
 20. The method of claim 13, wherein diffusion barrier properties of the one or more two-dimensional diffusion barrier layers is about equal to a bilayer of TaN/Ta having a thickness of about 5 nm. 